US 12,283,634 B2
Semiconductor device and manufacturing method thereof
Shunpei Yamazaki, Tokyo (JP); Junichi Koezuka, Tochigi (JP); Masami Jintyou, Tochigi (JP); and Yukinori Shima, Gunma (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Mar. 21, 2024, as Appl. No. 18/612,650.
Application 15/907,315 is a division of application No. 14/610,336, filed on Jan. 30, 2015, granted, now 9,929,279, issued on Mar. 27, 2018.
Application 18/612,650 is a continuation of application No. 18/134,185, filed on Apr. 13, 2023, granted, now 11,942,555, issued on Mar. 26, 2024.
Application 18/134,185 is a continuation of application No. 17/320,557, filed on May 14, 2021, granted, now 11,640,996, issued on May 2, 2023.
Application 17/320,557 is a continuation of application No. 16/658,196, filed on Oct. 21, 2019, granted, now 11,011,648, issued on May 18, 2021.
Application 16/658,196 is a continuation of application No. 15/907,315, filed on Feb. 28, 2018, granted, now 10,680,116, issued on Jun. 9, 2020.
Claims priority of application No. 2014-020061 (JP), filed on Feb. 5, 2014; and application No. 2014-041446 (JP), filed on Mar. 4, 2014.
Prior Publication US 2024/0313122 A1, Sep. 19, 2024
Int. Cl. H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 29/42384 (2013.01); H01L 29/66969 (2013.01); H01L 29/78606 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a pixel portion, the pixel portion comprising:
a first gate electrode over a substrate;
a first gate insulating layer over the first gate electrode;
a first oxide semiconductor layer over the first gate insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode and a drain electrode over and in contact with the second oxide semiconductor layer;
a pixel electrode electrically connected to one of the source electrode and the drain electrode; and
a liquid crystal layer over the pixel electrode,
wherein the first oxide semiconductor layer comprises In, Ga, and Zn at an atomic ratio of 1:1:1,
wherein the second oxide semiconductor layer comprises In, Ga, and Zn at an atomic ratio of 1:3:6, and
wherein the first oxide semiconductor layer is thinner than the second oxide semiconductor layer.