US 12,283,633 B2
Composite and transistor
Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 15, 2023, as Appl. No. 18/540,987.
Application 18/540,987 is a continuation of application No. 17/884,717, filed on Aug. 10, 2022, granted, now 11,869,980.
Application 17/884,717 is a continuation of application No. 16/690,755, filed on Nov. 21, 2019, granted, now 11,417,771, issued on Aug. 16, 2022.
Application 16/690,755 is a continuation of application No. 15/443,052, filed on Feb. 27, 2017, granted, now 10,516,060, issued on Dec. 24, 2019.
Claims priority of application No. 2016-048802 (JP), filed on Mar. 11, 2016.
Prior Publication US 2024/0113231 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 23/522 (2006.01); H01L 23/544 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 23/5226 (2013.01); H01L 23/544 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H01L 2223/5446 (2013.01)] 33 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a transistor comprising:
a gate electrode;
a gate insulating film; and
an oxide semiconductor layer comprising indium, an element M, and zinc,
wherein the element M is one or more of Al, Ga, Y and Sn,
wherein the oxide semiconductor layer comprises a first region and a second region and a third region,
wherein an atomic ratio of In to the element M in the second region is greater than an atomic ratio of In to the element M in the first region,
wherein an atomic ratio of In to the element M in the third region is greater than the atomic ratio of In to the element M in the first region, and
wherein the second region and the third region are surrounded with the first region.