US 12,283,627 B2
Semiconductor device having a gate insulating layer
Takui Sakaguchi, Kyoto (JP); Masatoshi Aketa, Kyoto (JP); and Yuki Nakano, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Jul. 17, 2023, as Appl. No. 18/353,109.
Application 18/353,109 is a continuation of application No. 17/371,752, filed on Jul. 9, 2021, granted, now 11,749,749.
Application 17/371,752 is a continuation of application No. 16/479,886, granted, now 11,088,272, issued on Aug. 10, 2021, previously published as PCT/JP2018/002357, filed on Jan. 25, 2018.
Claims priority of application No. 2017-011609 (JP), filed on Jan. 25, 2017.
Prior Publication US 2023/0361210 A1, Nov. 9, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7806 (2013.01) [H01L 21/049 (2013.01); H01L 29/0696 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor layer having a first main surface on one side and a second main surface on the other side;
a unit cell including a well region of a second conductivity type formed in a surface layer portion of the first main surface and a first conductivity type region formed in a surface layer portion of the well region;
a gate electrode layer that faces the well region across a gate insulating layer; and
a buried portion of an insulating material formed between the gate electrode layer and the first conductivity type region, the buried portion is in contact with the gate insulating layer and a thickness of the buried portion is more than a thickness of the gate insulating layer.