US 12,283,626 B2
Semiconductor device
Aryan Afzalian, Chastre (BE)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Feb. 5, 2024, as Appl. No. 18/432,812.
Application 17/333,743 is a division of application No. 16/358,394, filed on Mar. 19, 2019, granted, now 11,024,729, issued on Jun. 1, 2021.
Application 18/432,812 is a continuation of application No. 17/333,743, filed on May 28, 2021, granted, now 11,894,451, issued on Feb. 6, 2024.
Claims priority of provisional application 62/737,861, filed on Sep. 27, 2018.
Prior Publication US 2024/0178308 A1, May 30, 2024
Int. Cl. H01L 29/775 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/775 (2013.01) [H01L 29/1054 (2013.01); H01L 29/66439 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
etching a substrate to form a core structure protruding out of a plane of the substrate;
forming shallow trench isolation (STI) features on opposite sides of the core structure;
doping the substrate and a lower portion of the core structure to form a first source/drain region with a first doping concentration;
growing a barrier layer on an upper portion of the core structure;
forming a first spacer covering the STI features and covering the lower portion of core structure;
forming a shell wrapping the upper portion of the core structure and the barrier layer, wherein the shell and the upper portion of the core structure have different doping conductivity types;
forming a second source/drain region with a second doping concentration over the shell, wherein the first doping concentration and the second doping concentration are different from each other; and
forming a first gate around the shell.