| CPC H01L 29/66795 (2013.01) [H01L 21/02315 (2013.01); H01L 21/02334 (2013.01); H01L 21/823431 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |

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1. A method of manufacturing a semiconductor device, the method comprising:
forming a first fin structure and a second fin structure and forming a first wall fin structure and a second wall fin structure over a substrate, so that the first fin structure and the second fin structure are disposed between the first wall fin structure and the second wall fin structure, and lower portions of the first and second fin structures and the first and second wall fin structures are embedded in an isolation insulating layer and upper portions of the first and second fin structures and the first and second wall fin structures are exposed from the isolation insulating layer;
forming a sidewall spacer layer on sidewalls of the first and second fin structures and the first and second wall fin structures, wherein:
the sidewall spacer layer includes a first dielectric layer and a second dielectric layer formed over the first dielectric layer and made of a different material than the first dielectric layer,
the first dielectric layer is made of SiOCN, and
a carbon concentration of the first dielectric layer is in a range from 6 atomic % to 18 atomic %, and an oxygen concentration of the first dielectric layer is in a range from 20 atomic % to 45 atomic %;
recessing source/drain regions of the first and second fin structures; and
forming an epitaxial source/drain structure over the recessed first and second fin structures,
wherein a width W1 of the first and second fin structures is smaller than a thickness W2 of the sidewall spacer layer.
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