US 12,283,623 B2
Semiconductor structure and method for manufacturing thereof
Chih-Hsuan Lin, Hsinchu (TW); Hsi Chung Chen, Tainan (TW); and Chih-Teng Liao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinch (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,632.
Application 18/446,632 is a division of application No. 17/303,794, filed on Jun. 8, 2021.
Claims priority of provisional application 62/706,405, filed on Aug. 14, 2020.
Claims priority of provisional application 63/072,503, filed on Aug. 31, 2020.
Prior Publication US 2023/0387255 A1, Nov. 30, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01)
CPC H01L 29/6656 (2013.01) [H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
forming an isolation stack over a substrate having a conductive region and an isolation region at a first surface of the substrate, and having a conductive region contact and a gate structure over the conductive region and the isolation region, respectively, wherein the gate structure is laterally surrounded by a spacer;
forming a first recess traversing the isolation stack over the gate structure;
forming a second recess traversing the isolation stack over the conductive region contact;
forming a recap layer over the isolation stack, the first recess and the second recess;
removing a bottom portion of the recap layer in the first recess and the second recess, and thereby a top surface of the gate structure is exposed from the recap layer; and
forming a first via contact and a second via contact in the first recess and the second recess, respectively.