US 12,283,622 B2
Semiconductor device and method
De-Wei Yu, Ping-tung (TW); Cheng-Po Chau, Tainan (TW); and Yun Chen Teng, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/342,146.
Application 17/121,343 is a division of application No. 16/050,234, filed on Jul. 31, 2018, granted, now 10,868,137, issued on Dec. 15, 2020.
Application 18/342,146 is a continuation of application No. 17/121,343, filed on Dec. 14, 2020, granted, now 11,728,406.
Prior Publication US 2023/0352563 A1, Nov. 2, 2023
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 21/02359 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/0262 (2013.01); H01L 21/02645 (2013.01); H01L 21/02664 (2013.01); H01L 21/32055 (2013.01); H01L 21/32137 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device comprising:
depositing a dielectric layer over a semiconductor fin;
depositing a dummy gate seed layer on the dielectric layer;
reflowing the dummy gate seed layer, wherein the reflowing the dummy gate seed layer decreases a first thickness of the dummy gate seed layer on a top surface of the semiconductor fin exposing a first portion of the dielectric layer and increases a second thickness of the dummy gate seed layer adjacent a second portion of the dielectric layer; and
etching the first portion of the dielectric layer, wherein the etching the dielectric layer forms a halogen-terminated surface in the first portion of the dielectric layer, wherein the second portion of the dielectric layer is not etched and is free from the halogen-terminated surface.