US 12,283,620 B2
Method for manufacturing semiconductor device
Yosuke Maegawa, Nisshin (JP); and Yohei Iwahashi, Nisshin (JP)
Assigned to DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed by DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed on Nov. 11, 2022, as Appl. No. 18/054,568.
Claims priority of application No. 2021-191978 (JP), filed on Nov. 26, 2021.
Prior Publication US 2023/0170399 A1, Jun. 1, 2023
Int. Cl. H01L 21/027 (2006.01); H01L 21/04 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66068 (2013.01) [H01L 21/0475 (2013.01); H01L 29/7813 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device having a plurality of trench gate structures, the method comprising:
preparing a semiconductor substrate having one surface;
arranging a mask on the one surface of the semiconductor substrate;
forming a plurality of opening portions in the mask by patterning the mask so as to expose a plurality of planned formation regions of the semiconductor substrate where a plurality of trenches are to be formed;
forming the plurality of trenches, which extend in a longitudinal direction along a planar direction of the semiconductor substrate, in the semiconductor substrate adjacent to the one surface, by performing a first etching using the mask;
forming a rounded portion at an opening end portion of each of the plurality of trenches by performing a second etching in a state where the mask is arranged and under a condition that a selectivity of the mask is higher than that of the semiconductor substrate; and
arranging a gate insulating film and a gate electrode in each of the plurality of trenches thereby to form the plurality of trench gate structures.