| CPC H01L 29/42372 (2013.01) [H01L 21/28088 (2013.01); H01L 21/28097 (2013.01); H01L 29/0649 (2013.01); H01L 29/1033 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01); H01L 29/7853 (2013.01)] | 20 Claims |

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1. A method, comprising:
forming a semiconductor fin;
forming a gate dielectric layer over the semiconductor fin;
depositing a p-type work function metal layer over the gate dielectric layer;
depositing an n-type work function metal layer over the p-type work function metal layer; and
forming a gate electrode over the n-type work function metal layer, wherein a concentration of a work function material in the n-type work function metal layer increases from a first value to a peak value and then decreases from the peak value to a second value, and wherein the concentration of the work function material in the n-type work function metal layer at an interface of the gate electrode and the n-type work function metal layer has a first non-zero value lower than about 35%.
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