US 12,283,601 B2
Method for manufacturing TFT substrate and TFT substrate thereof
Yongqi Deng, Huizhou (CN); and Li Chai, Huizhou (CN)
Assigned to Huizhou China Star Optoelectronics Display Co., Ltd., Huizhou (CN); and Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
Appl. No. 17/621,941
Filed by Huizhou China Star Optoelectronics Display Co., Ltd., Huizhou (CN); and Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
PCT Filed Nov. 8, 2021, PCT No. PCT/CN2021/129362
§ 371(c)(1), (2) Date Dec. 22, 2021,
PCT Pub. No. WO2023/070741, PCT Pub. Date May 4, 2023.
Claims priority of application No. 202111274505.3 (CN), filed on Oct. 29, 2021.
Prior Publication US 2024/0266360 A1, Aug. 8, 2024
Int. Cl. H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01)
CPC H01L 27/1244 (2013.01) [H01L 27/1255 (2013.01); H01L 27/127 (2013.01); H01L 27/1288 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for manufacturing thin-film transistor (TFT) substrate, comprising:
step B1: forming a photoresist layer on a semi-finished substrate, wherein the semi-finished substrate comprises a first metal layer, an insulating layer disposed on the first metal layer, and a semiconductor layer disposed on the insulating layer, the photoresist layer is disposed on the semiconductor layer, and the semi-finished substrate has a first region, a second region, and a third region;
step B2: patterning the photoresist layer to expose the semiconductor layer in the third region, where a remaining portion of the photoresist forms a first etching barrier layer corresponding to the first region and where another remaining portion of the photoresist forms a second etching barrier layer corresponding to the second region, wherein a thickness of the first etching barrier layer is less than a thickness of the second etching barrier layer;
step B3: etching the semiconductor layer in the third region under the shielding of the first etching barrier layer and the second etching barrier layer;
step B4: peeling off the first etching barrier layer to expose the semiconductor layer in the first region;
Step B5: etching the semiconductor layer and the insulating layer under the shielding of the second etching barrier layer to remove the semiconductor layer disposed corresponding to the first region, such that a thickness of the insulating layer in the third region is less than a thickness of the insulating layer in the first region.