US 12,283,600 B2
Semiconductor device comprising transistor, load, and wiring configured to supply power supply potential to the load
Hitoshi Kunitake, Kanagawa (JP); and Kazuki Tsuda, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/615,780
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed May 22, 2020, PCT No. PCT/IB2020/054865
§ 371(c)(1), (2) Date Dec. 1, 2021,
PCT Pub. No. WO2020/245692, PCT Pub. Date Dec. 10, 2020.
Claims priority of application No. 2019-106637 (JP), filed on Jun. 7, 2019.
Prior Publication US 2022/0238560 A1, Jul. 28, 2022
Int. Cl. H01L 27/14 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/124 (2013.01) [H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01)] 3 Claims
OG exemplary drawing
 
3. A semiconductor device, comprising:
a first transistor, a second transistor, a load, and a wiring configured to supply a power supply potential to the load,
wherein a semiconductor layer of the first transistor comprises an oxide semiconductor,
wherein a semiconductor layer of the second transistor comprises an oxide semiconductor,
wherein a first gate of the first transistor comprises a region overlapping with a second gate of the first transistor with the semiconductor layer of the first transistor therebetween,
wherein a first gate of the second transistor comprises a region overlapping with a second gate of the second transistor with the semiconductor layer of the second transistor therebetween,
wherein a source and a drain of the first transistor are electrically connected to the wiring,
wherein the first gate of the first transistor and the second gate of the first transistor are supplied with a reference potential,
wherein a source and a drain of the second transistor are supplied with a reference potential,
wherein the first gate of the second transistor and the second gate of the second transistor are electrically connected to the wiring,
wherein the semiconductor layer of the first transistor comprises a region overlapping with the wiring, and
wherein the semiconductor layer of the second transistor comprises a region overlapping with the wiring.