US 12,283,599 B2
Semiconductor device
Shunpei Yamazaki, Tokyo (JP); Jun Koyama, Kanagawa (JP); and Kiyoshi Kato, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Sep. 5, 2023, as Appl. No. 18/242,210.
Application 18/242,210 is a continuation of application No. 17/949,436, filed on Sep. 21, 2022, granted, now 11,825,665.
Application 17/949,436 is a continuation of application No. 16/779,774, filed on Feb. 3, 2020, granted, now 11,456,296, issued on Sep. 27, 2022.
Application 16/779,774 is a continuation of application No. 15/995,204, filed on Jun. 1, 2018, granted, now 10,553,589, issued on Feb. 4, 2020.
Application 15/995,204 is a continuation of application No. 15/157,565, filed on May 18, 2016, granted, now 9,991,265, issued on Jun. 5, 2018.
Application 15/157,565 is a continuation of application No. 13/905,178, filed on May 30, 2013, granted, now 9,349,735, issued on May 24, 2016.
Application 13/905,178 is a continuation of application No. 12/976,564, filed on Dec. 22, 2010, granted, now 8,455,868, issued on Jun. 4, 2013.
Claims priority of application No. 2009-296202 (JP), filed on Dec. 25, 2009.
Prior Publication US 2023/0413587 A1, Dec. 21, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01); H10B 41/20 (2023.01); H10B 41/70 (2023.01); G11C 13/00 (2006.01); H01L 49/02 (2006.01); H10B 10/00 (2023.01)
CPC H01L 27/1225 (2013.01) [H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10B 12/00 (2023.02); H10B 41/20 (2023.02); H10B 41/70 (2023.02); G11C 13/0007 (2013.01); G11C 13/003 (2013.01); G11C 2213/79 (2013.01); H01L 28/40 (2013.01); H10B 10/00 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells arranged in a matrix;
a first driver circuit electrically connected to a bit line; and
a second driver circuit electrically connected to a word line,
wherein each of the plurality of memory cells comprises a first transistor and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the bit line,
wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor,
wherein a gate electrode of the first transistor is electrically connected to the word line,
wherein the first transistor comprises a channel formation region in an oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a crystal,
wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer,
wherein a potential is supplied to the one electrode of the capacitor by turning on the first transistor,
wherein the potential supplied to the capacitor is held by turning off the first transistor,
wherein at least one of the first driver circuit and the second driver circuit comprises a second transistor, and
wherein the second transistor comprises silicon in a channel formation region.