US 12,283,596 B2
Semiconductor device and manufacturing method thereof
Kuo-Pi Tseng, Hsinchu (TW); De-Fang Chen, Hsinchu (TW); and Chao-Cheng Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 7, 2023, as Appl. No. 18/348,531.
Application 18/348,531 is a continuation of application No. 17/230,295, filed on Apr. 14, 2021, granted, now 11,742,353.
Prior Publication US 2023/0361122 A1, Nov. 9, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/3065 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/3065 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a substrate;
a channel layer over the substrate;
a gate structure across the channel layer;
a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite sides of the channel layer and connected to the channel layer; and
a bottom dielectric structure between the first source/drain epitaxial structure and the substrate, wherein a maximum width of the first source/drain epitaxial structure is greater than or equal to a maximum width of the bottom dielectric structure in a cross-sectional view, and the bottom dielectric structure is in contact with the substrate.