US 12,283,595 B2
Integration of multiple transistors having fin and mesa structures
Sung-Hsin Yang, Tainan (TW); Ru-Shang Hsiao, Jhubei (TW); Ching-Hwanq Su, Tainan (TW); Chen-Bin Lin, Tainan (TW); and Wen-Hsin Chan, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 17, 2022, as Appl. No. 17/655,321.
Claims priority of provisional application 63/278,514, filed on Nov. 12, 2021.
Prior Publication US 2023/0154922 A1, May 18, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/30604 (2013.01); H01L 21/308 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first plurality of etching masks over a semiconductor substrate;
forming a second plurality of etching masks over the semiconductor substrate;
etching the semiconductor substrate using the first plurality of etching masks and the second plurality of etching masks to form a plurality of semiconductor strips and a plurality of mesa structures, respectively;
forming a first plurality of dielectric isolation regions between the plurality of semiconductor strips;
forming a second plurality of dielectric isolation regions encircling the plurality of mesa structures, wherein the forming the second plurality of dielectric isolation regions comprises:
performing a first etching process to etch the semiconductor substrate, wherein first recesses and upper portions of second recesses are formed, and wherein the first plurality of dielectric isolation regions and upper portions of the second plurality of dielectric isolation regions are in the first recesses and the upper portions of the second recesses, respectively; and
performing a second etching process to etch the semiconductor substrate, wherein the second recesses are extended down, and wherein lower portions of the second plurality of dielectric isolation regions are formed in extended portions of the second recesses;
recessing the first plurality of dielectric isolation regions, wherein top portions of a first group of semiconductor strips in the plurality of semiconductor strips protrude higher than the first plurality of dielectric isolation regions to form a first plurality of protruding semiconductor fins;
forming a first gate dielectric on top surfaces and sidewalls of the first plurality of protruding semiconductor fins;
forming a first gate electrode over the first gate dielectric, wherein the first gate dielectric and the first gate electrode form parts of a first transistor;
forming a second gate dielectric over a first mesa structure in the plurality of mesa structures; and
forming a second gate electrode over the second gate dielectric, wherein the second gate dielectric and the second gate electrode form parts of a second transistor.