US 12,283,590 B2
Integrated circuit and manufacturing method thereof
Xin-Yong Wang, Shanghai (CN); Li-Chun Tien, Tainan (TW); and Chih-Liang Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and TSMC China Company Limited, Shanghai (CN)
Filed on Feb. 5, 2024, as Appl. No. 18/432,543.
Application 17/873,935 is a division of application No. 17/108,635, filed on Dec. 1, 2020, granted, now 11,469,221, issued on Oct. 11, 2022.
Application 18/432,543 is a continuation of application No. 17/873,935, filed on Jul. 26, 2022, granted, now 11,929,361.
Claims priority of application No. 202011271727.5 (CN), filed on Nov. 13, 2020.
Prior Publication US 2024/0178215 A1, May 30, 2024
Int. Cl. H01L 27/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 27/0207 (2013.01) [H01L 21/76816 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a substrate;
a metal layer over the substrate;
a semiconductor device over the metal layer, wherein the semiconductor device comprises a first transistor and a second transistor vertically above the first transistor;
an interconnect structure over the metal layer and adjacent to the semiconductor device;
a first via between and electrically connected to the metal layer and the semiconductor device; and
a second via between and electrically connected to the metal layer and the interconnect structure.