US 12,283,586 B2
Integrated circuit device, method and system
Wei-Ling Chang, Hsinchu (TW); Chih-Liang Chen, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Chia-Tien Wu, Hsinchu (TW); and Jia-Hong Gao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/462,974.
Prior Publication US 2023/0067734 A1, Mar. 2, 2023
Int. Cl. H01L 27/02 (2006.01); G06F 30/392 (2020.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/118 (2006.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); H01L 21/76898 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 27/11807 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a circuit region;
a lower metal layer over the circuit region in a thickness direction of the IC device, and comprising a plurality of lower conductive patterns elongated along a first axis; and
an upper metal layer over the lower metal layer in the thickness direction, and comprising:
a plurality of upper conductive patterns elongated along a second axis transverse to the first axis, the plurality of upper conductive patterns comprising at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region, and
a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern other than the output among the plurality of upper conductive patterns, the first lateral upper conductive pattern overlapping, in the thickness direction, and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns,
wherein, along the second axis, a dimension of the first lower conductive pattern is smaller than a dimension of the first lateral upper conductive pattern overlapping the first lower conductive pattern.