US 12,283,578 B2
Semiconductor package and method of fabricating same
Jeong Hyun Lee, Seoul (KR); Hwan Pil Park, Hwaseong-si (KR); and Jong Bo Shim, Asan-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 31, 2022, as Appl. No. 17/710,830.
Claims priority of application No. 10-2021-0057364 (KR), filed on May 3, 2021.
Prior Publication US 2022/0352130 A1, Nov. 3, 2022
Int. Cl. H01L 25/16 (2023.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/162 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 25/165 (2013.01); H01L 24/48 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/3201 (2013.01); H01L 2224/32059 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32265 (2013.01); H01L 2224/3303 (2013.01); H01L 2224/33051 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3511 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a substrate including a first insulating layer and a first conductive pattern in the first insulating layer;
a first semiconductor chip on the substrate;
an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate, and including a second insulating layer and a second conductive pattern in the second insulating layer;
a first element between the first semiconductor chip and the interposer, the first element comprising
a first face fixed to an upper surface of the first semiconductor chip with a non-conductive adhesive layer between the first face and the upper surface of the first semiconductor chip, and
a second face opposite the first face, the second face having contacts electrically connected to the interposer;
a connection member between the substrate and the interposer; and
a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.