| CPC H01L 25/0657 (2013.01) [G06F 15/7825 (2013.01); H01L 23/53204 (2013.01); H01L 24/08 (2013.01); H01L 24/83 (2013.01); H01L 25/18 (2013.01); G06F 2015/763 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06524 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01)] | 18 Claims |

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1. A network to horizontally and vertically route electrical communications between components of stacked device layers of a 3D system on chip (SoC), the network comprising:
a first network layer disposed between a first device layer and a second device layer, the first device layer comprising one or more first components and the second device layer comprising one or more second components;
a third device layer directly bonded to the second device layer, the third device layer comprising one or more third components in direct electrical communication with the one or more second components; and
a second network layer disposed between the third device layer and a fourth device layer comprising one or more fourth components, wherein the first network layer and the second network layer route electrical communications between at least one of the first components and one or more of the fourth components.
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