US 12,283,571 B1
Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor
Rajeev Kumar Dokania, Beaverton, OR (US); Sasikanth Manipatruni, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Debo Olaosebikan, San Francisco, CA (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Apr. 14, 2021, as Appl. No. 17/230,889.
Application 17/230,889 is a continuation of application No. 16/428,885, filed on May 31, 2019, granted, now 11,043,472.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H10B 41/42 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 23/49811 (2013.01); H01L 23/49894 (2013.01); H01L 23/5389 (2013.01); H10B 41/42 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an interposer;
a first die having a first surface and a second surface opposite to the first surface, the first surface on the interposer, wherein the first die comprises a dynamic random-access memory (DRAM) having bit-cells, wherein the first die includes first active devices closer to the second surface than the first surface, and wherein the first die does not have a matrix multiplier;
a second die stacked over the first die, wherein the second die substantially overlaps the first die, the second die having a third surface and a fourth surface opposite the third surface, wherein the third surface faces the second surface, wherein the second die comprises one or more controller circuitries coupled to the DRAM of the first die, wherein the second die includes second active devices, wherein the second active devices are closer to the fourth surface than the third surface, and wherein the second die does not have a matrix multiplier; and
a third die stacked over the second die, the third die being an uppermost die, wherein the third dies substantially overlaps the second die, the third die having a fifth surface and a sixth surface opposite to the fifth surface, wherein the fifth surface faces the fourth surface, wherein the third die comprises processing cores, wherein at least one processing core includes a matrix multiplier coupled to the DRAM of the first die, wherein the third die includes third active devices, and wherein the third active devices are closer to the fifth surface than the sixth surface.