US 12,283,570 B2
Package structure
Ming-Fa Chen, Taichung (TW); Hsien-Wei Chen, Hsinchu (TW); and Sung-Feng Yeh, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 23, 2023, as Appl. No. 18/305,370.
Application 18/305,370 is a continuation of application No. 17/199,443, filed on Mar. 12, 2021, granted, now 11,676,942.
Prior Publication US 2023/0307417 A1, Sep. 28, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0655 (2013.01) [H01L 22/14 (2013.01); H01L 23/3128 (2013.01); H01L 24/24 (2013.01); H01L 25/50 (2013.01); H01L 2224/24225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a semiconductor structure, comprising:
a first die, wherein the first die comprises: a first interconnection structure disposed over a first substrate; and a first conductive pad disposed on and electrically connected to the first interconnection structure and embedded by a first passivation layer;
a dielectric layer, laterally wrapping around the first die, wherein a top surface of the dielectric layer is flush with a top surface of the first passivation layer; and
a second interconnection structure, disposed on the first die and the dielectric layer, wherein the second interconnection structure comprises a conductive via extending from a conductive line, passing through the first passivation layer and landing on the first conductive pad of the first die, wherein a top surface the conductive via is coplanar with the top surface of the first passivation layer;
an encapsulant, laterally encapsulating the semiconductor structure; and
a redistribution layer structure, disposed on the semiconductor structure and the encapsulant.