US 12,283,568 B2
Wafer bonding alignment
Hsi-Cheng Hsu, Taichung (TW); Jui-Chun Weng, Taipei (TW); Ching-Hsiang Hu, Taipei (TW); Ji-Hong Chiang, Changhua (TW); Kuo-Hao Lee, Hsinchu (TW); Chia-Yu Lin, Taoyuan (TW); Chia-Chun Hung, Chiayi (TW); Yen-Chieh Tu, Taichung (TW); Chien-Tai Su, Hsinchu (TW); and Hsin-Yu Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 5, 2023, as Appl. No. 18/347,067.
Application 18/347,067 is a division of application No. 17/249,758, filed on Mar. 11, 2021, granted, now 11,742,320.
Prior Publication US 2023/0352445 A1, Nov. 2, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/544 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/94 (2013.01) [H01L 23/544 (2013.01); H01L 23/562 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by a processing device, information associated with a plurality of operations to bond a first plurality of semiconductor devices on a first plurality of substrates with a second plurality of semiconductor devices on a second plurality of substrates;
generating, by the processing device and based on the information associated with the plurality of operations, thermal expansion data for the first plurality of substrates and thermal expansion data for the second plurality of substrates;
determining, by the processing device and based on the thermal expansion data for the first plurality of substrates and the thermal expansion data for the second plurality of substrates, adjusted widths for a plurality of scribe lines of at least one of a third substrate or a fourth substrate; and
providing, by the processing device, an indication of the adjusted widths to one or more semiconductor processing tools for forming the plurality of scribe lines based on the adjusted widths.