US 12,283,564 B2
Semiconductor structure and manufacturing method thereof
Min-Feng Kao, Chiayi (TW); Dun-Nian Yaung, Taipei (TW); Jen-Cheng Liu, Hsin-Chu (TW); Hsing-Chih Lin, Tainan (TW); and Zheng-Xun Li, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 14, 2023, as Appl. No. 18/352,270.
Application 18/352,270 is a continuation of application No. 17/226,081, filed on Apr. 9, 2021, granted, now 11,756,920.
Prior Publication US 2023/0361075 A1, Nov. 9, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/80 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/32146 (2013.01); H01L 2224/8038 (2013.01); H01L 2224/80894 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a top tier;
a bottom tier, comprising a first semiconductor substrate and a first front-side bonding structure overlying the first semiconductor substrate; and
a middle tier, between and electrically coupled to the top tier and the bottom tier, the middle tier comprising:
a second semiconductor substrate; and
a second front-side bonding structure overlying the second semiconductor substrate, a first bonding feature of the second front-side bonding structure comprising a first bonding via, a first bonding contact overlying the first bonding via, and a barrier layer interface between a bottom of the first bonding contact and a top of the first bonding via.