US 12,283,558 B2
Half-bridge circuit package structure
Kuo-Lun Huang, Hsinchu (TW)
Assigned to MOTOR SEMICONDUCTOR CO., LTD., Hsinchu County (TW)
Filed by Motor Semiconductor Co., Ltd., Hsinchu County (TW)
Filed on Dec. 14, 2021, as Appl. No. 17/549,910.
Prior Publication US 2023/0187394 A1, Jun. 15, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/06 (2013.01) [H01L 2224/0603 (2013.01); H01L 2224/0613 (2013.01); H01L 2224/48177 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A half-bridge circuit package structure comprising:
a chip pad;
a substrate bonded to the chip pad, wherein the substrate includes a first metal island electrically connected to a high side ground pin;
a driving chip disposed on the chip pad, wherein the driving chip includes a ground pad, a low side output pad, a high side ground pad, and a high side output pad, wherein the driver chip is electrically connected to a high side power pin by a high side power pad, to an input power pin by an input power pad, to a high side input pin by a high side input pad, and to a low side input pin by a low side input pad;
an upper bridge switch bonded to the substrate, wherein the upper bridge switch includes a first enhancement mode transistor and a first depletion mode transistor, wherein a gate pad of the first enhancement mode transistor is electrically connected to the high side output pad, a source pad of the first enhancement mode transistor is electrically connected to the first metal island and the high side ground pad, a gate pad of the first depletion mode transistor is electrically connected to the source pad of the first enhancement mode transistor, a source pad of the first depletion mode transistor is electrically connected to a drain pad of the first enhancement mode transistor, and a drain pad of the first depletion mode transistor is electrically connected to a power pin; and
a lower bridge switch bonded to the substrate, wherein the lower bridge switch includes a second enhancement mode transistor and a second depletion mode transistor, wherein a gate pad of the second enhancement mode transistor is electrically connected to the low side output pad, a source pad of the second enhancement mode transistor is electrically connected to a common contact pin, a gate pad of the second depletion mode transistor is electrically connected to the source pad of the second enhancement mode transistor, a source pad of the second depletion mode transistor is electrically connected to a drain pad of the second enhancement mode transistor, and a drain pad of the second depletion mode transistor is electrically connected to the high side ground pin.