US 12,283,555 B2
Semiconductor packages
Bilge Bayrakci, Istanbul (TR); Abdullah Celik, Istanbul (TR); Winslow Round, Amesbury, MA (US); Santosh Anil Kudtarkar, Ayer, MA (US); Yusuf Atesal, Istanbul (TR); and Turusan Kolcuoglu, Arlington, MA (US)
Assigned to Analog Devices International Unlimited Company, Co. Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on Aug. 8, 2018, as Appl. No. 16/058,922.
Claims priority of provisional application 62/647,549, filed on Mar. 23, 2018.
Prior Publication US 2019/0295968 A1, Sep. 26, 2019
Int. Cl. H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H05K 3/32 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 23/147 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/37 (2013.01); H01L 24/45 (2013.01); H01L 25/0657 (2013.01); H05K 1/0243 (2013.01); H05K 1/183 (2013.01); H05K 3/321 (2013.01); H01L 23/49822 (2013.01); H01L 24/05 (2013.01); H01L 24/32 (2013.01); H01L 24/40 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6616 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/293 (2013.01); H01L 2224/40227 (2013.01); H01L 2224/45014 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/48472 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/83104 (2013.01); H01L 2224/92125 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19107 (2013.01); H05K 3/32 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A package comprising:
a carrier comprising a first conductive layer on a first exterior side and a second conductive layer on a second exterior side opposite the first exterior side, wherein the carrier comprises a ceramic substrate or a semiconductor substrate, and the first conductive layer comprises a first portion having wire bonding pads configured to electrically connect the package with an external substrate or device;
a semiconductor die flip-chip mounted on the first exterior side of the carrier, a trace of the first conductive layer extending continuously on the first exterior side of the carrier from a first wire bonding pad of the wire bonding pads to the semiconductor die; and
a conductive pillar between the semiconductor die and the carrier, a first portion of the conductive pillar extends from a surface of the carrier and a second portion of the conductive pillar extends from a surface of the semiconductor die,
wherein the carrier comprises an electrical ground via electrically connecting the semiconductor die and the second conductive layer, the first conductive layer comprises a second portion configured to distribute ground connections from the semiconductor die to an area on the first exterior side of the carrier wider than an area of the semiconductor die, and the semiconductor die is positioned at least partially over the second portion of the first conductive layer.