US 12,283,553 B2
Semiconductor die with warpage release layer structure in package and fabricating method thereof
Chin-Hua Wang, New Taipei (TW); Kuang-Chun Lee, New Taipei (TW); Shu-Shen Yeh, Taoyuan (TW); Tsung-Yen Lee, Changhua County (TW); Po-Yao Lin, Hsinchu County (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 3, 2023, as Appl. No. 18/311,434.
Application 18/311,434 is a continuation of application No. 17/370,299, filed on Jul. 8, 2021, granted, now 11,694,974.
Prior Publication US 2023/0275038 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/3736 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a first semiconductor die bonded over an interposer substrate; and
a warpage release layer structure, comprising:
a first organic material layer covering an upper surface of the first semiconductor die; and
a first metal layer covering an upper surface of the first organic material layer, wherein the first metal layer has a planar shape that is the same as a planar shape of the first semiconductor die, as viewed in a top-view perspective.