US 12,283,549 B2
High density interconnection using fanout interposer chiplet
Jun Zhai, Cupertino, CA (US); Chonghua Zhong, Cupertino, CA (US); and Kunzhong Hu, Cupertino, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 1, 2023, as Appl. No. 18/163,033.
Application 18/163,033 is a continuation of application No. 17/166,795, filed on Feb. 3, 2021, granted, now 11,594,494.
Application 17/166,795 is a continuation of application No. 15/817,054, filed on Nov. 17, 2017, granted, now 10,943,869, issued on Mar. 9, 2021.
Claims priority of provisional application 62/517,789, filed on Jun. 9, 2017.
Prior Publication US 2023/0223348 A1, Jul. 13, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/16 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 23/31 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5385 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 23/16 (2013.01); H01L 23/49833 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 25/0655 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/4857 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 25/18 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/92225 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/37001 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A package comprising:
an encapsulation layer;
a first component and a second component embedded within the encapsulation layer;
a redistribution layer (RDL) on a first side of the encapsulation layer and directly on and in electrical contact with a first plurality of terminals of the first and second components and a second plurality of terminals of the first component and the second components;
a plurality of conductive pillars extending from a first side of the RDL; and
an interposer chiplet mounted on the first side of the RDL;
wherein the RDL comprises a first area of fan out interconnect routing interconnected with the plurality of conductive pillars, and a second area of routing interconnected with the interposer chiplet, and second area of routing includes an arrangement of stacked vias and underbump metallurgy (UBM) pads on the stacked vias to interconnect the interposer chiplet with the first and second components;
wherein the first plurality of terminals of the first and second components is in electrical connection with the plurality of conductive pillars laterally adjacent the interposer chiplet, and the second plurality of terminals of first and second components is in electrical connection with the arrangement of stacked vias and UBM pads;
wherein the interposer chiplet is bonded directly to the UBM pads of the arrangement of stacked vias and UBM pads of the RDL with a first plurality of first solder bumps.