| CPC H01L 23/535 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 19 Claims |

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1. A semiconductor device, comprising:
a peripheral circuit structure on a lower substrate;
an upper substrate on the peripheral circuit structure; a stack structure on the upper substrate;
a memory vertical structure penetrating through a first stack portion of the stack structure; and
vertical pillars penetrating through a second stack portion of the stack structure,
wherein the second stack portion includes first layers and second layers alternately stacked in a vertical direction, wherein a material of the first layers is different from a material of the second layers,
wherein the second layers include a lower layer and an upper layer on the lower layer,
wherein the first layers include an intermediate layer between an upper surface of the lower layer and a lower surface of the upper layer,
wherein the upper layer includes a first portion and a second portion adjacent to the first portion,
wherein a lower surface of the first portion and a lower surface of the second portion are coplanar with each other,
wherein an upper surface of the second portion is at a higher level than an upper surface of the first portion,
wherein a thickness of the second portion is greater than a thickness of the first portion,
wherein at least one of the vertical pillars penetrates through the first portion of the upper layer, and wherein
the upper layer further includes a third portion,
the first portion is between the second portion and the third portion, and
a thickness of the third portion is greater than the thickness of the first portion.
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