US 12,283,545 B2
Package structure and method of manufacturing the same
Yung-Chi Chu, Kaohsiung (TW); Hung-Jui Kuo, Hsinchu (TW); Yu-Hsiang Hu, Hsinchu (TW); and Wei-Chih Chen, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/363,698.
Application 18/363,698 is a division of application No. 17/513,904, filed on Oct. 29, 2021, granted, now 11,862,560.
Application 17/513,904 is a continuation of application No. 16/352,843, filed on Mar. 14, 2019, granted, now 11,164,814, issued on Nov. 2, 2021.
Prior Publication US 2023/0378065 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5283 (2013.01) [H01L 21/563 (2013.01); H01L 21/76873 (2013.01); H01L 23/3128 (2013.01); H01L 23/5226 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/09 (2013.01); H01L 24/14 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/73203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a semiconductor die; and
a first redistribution circuit structure, disposed on and electrically coupled to the semiconductor die, and comprising:
a first build-up layer, comprising:
a first metallization layer;
a first seed layer sandwiched between the first metallization layer and the semiconductor die; and
a first dielectric layer, laterally covering the first metallization layer and the first seed layer, wherein a first portion of the first metallization layer is protruding out of the first dielectric layer,
wherein the first metallization layer has a first surface at the first portion protruding out the first dielectric layer and a second surface at a second portion being embedded in the first dielectric layer and opposite to the first portion, and a first lateral size of the first surface is less than a second lateral size of the second surface, wherein the first surface is free from the first seed layer, and the second surface is in contact with the first seed layer.