US 12,283,542 B2
Power supply line arrangement having power switch circuit
Hirotaka Takeno, Yokohama (JP); Atsushi Okamoto, Yokohama (JP); and Toshio Hino, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on Jan. 18, 2022, as Appl. No. 17/577,994.
Claims priority of application No. 2021-006440 (JP), filed on Jan. 19, 2021.
Prior Publication US 2022/0231053 A1, Jul. 21, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01); H10D 89/10 (2025.01)
CPC H01L 23/5226 (2013.01) [H01L 23/5286 (2013.01); H10D 89/10 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first power supply line formed in a first wiring layer and extending in a first direction in a plan view;
a second power supply line formed in the first wiring layer and extending in the first direction;
a third power supply line formed in a second wiring layer provided above the first wiring layer, extending in a second direction different from the first direction in the plan view, and connected to the first power supply line;
a fourth power supply line formed in the second wiring layer, extending in the second direction, and connected to the second power supply line;
a fifth power supply line formed in the first wiring layer; and
a first power switch circuit including a transistor provided between the first power supply line and the fifth power supply line,
wherein the transistor is positioned in the plan view overlapping one of or both of the third power supply line and the fourth power supply line, and
wherein the first power switch circuit includes
a first wiring formed in the second wiring layer, electrically connected to a source region of the transistor and to the fifth power supply line, extending in the second direction, and overlapping neither the third power supply line nor the fourth power supply line in the plan view above the transistor, and
a second wiring formed in the second wiring layer, electrically connected to a drain region of the transistor and to the third power supply line, extending in the second direction, and overlapping neither the third power supply line nor the fourth power supply line in the plan view above the transistor.