US 12,283,531 B2
Stacked semiconductor device test circuits and methods of use
Jen-Yuan Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 7, 2024, as Appl. No. 18/435,197.
Application 18/435,197 is a division of application No. 17/304,982, filed on Jun. 29, 2021, granted, now 11,935,798.
Claims priority of provisional application 63/201,298, filed on Apr. 22, 2021.
Prior Publication US 2024/0178078 A1, May 30, 2024
Int. Cl. H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/10 (2006.01)
CPC H01L 22/32 (2013.01) [H01L 22/22 (2013.01); H01L 22/34 (2013.01); H01L 23/481 (2013.01); H01L 24/32 (2013.01); H01L 25/105 (2013.01); H01L 2224/32146 (2013.01); H01L 2225/1047 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first plurality of circuits on a first substrate of a first die,
wherein the first plurality of circuits includes:
a test circuit, and
a control circuit;
forming a second plurality of circuits on a second substrate of a second die;
bonding the first die and the second die to form a stacked semiconductor device; and
performing, through the test circuit and using the control circuit to selectively isolate the first die and the second die, independent circuit probe tests of a subset of the first plurality of circuits and a subset of the second plurality of circuits,
wherein a first independent circuit probe test, of the subset of the first plurality of circuits, is performed when the first die and the second die are isolated, and
wherein a second independent circuit probe test, of the subset of the second plurality of circuits, is performed when the first die and the second die are electrically connected.