US 12,283,530 B2
Method for manufacturing a semiconductor structure for detecting vertical electrical leakage
Chun-Shun Huang, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/854,561.
Prior Publication US 2024/0006253 A1, Jan. 4, 2024
Int. Cl. H01L 21/66 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 22/32 (2013.01) [H01L 21/31116 (2013.01); H01L 21/32135 (2013.01); H01L 22/20 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor testing structure, comprising:
providing a substrate;
forming a first metal layer comprising a plurality of fingers extending along a first direction;
a dielectric structure disposed on the first metal layer; and
a plurality of second metal layers extending along a second direction different form the first direction;
forming a plurality of conductive layers on a lateral surface of each of the plurality of second metal layers;
wherein each of the conductive layers is on a sidewall of the dielectric structure;
wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer over the first dielectric layer;
wherein the first dielectric layer has a first upper surface in contact with the second dielectric layer and a second upper surface recessed from the first upper surface, a portion of the first dielectric layer is free from vertically overlapping the conductive layer, and a portion of the second upper surface of the first dielectric layer is free from vertically overlapping the conductive layer.