US 12,283,526 B2
Edge fin trim process
Jen-Chun Chou, Hsinchu (TW); Ren-Yu Chang, Hsinchu (TW); Che-Cheng Chang, New Taipei (TW); and Chen-Hsiang Lu, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 8, 2021, as Appl. No. 17/521,610.
Claims priority of provisional application 63/161,784, filed on Mar. 16, 2021.
Prior Publication US 2022/0301937 A1, Sep. 22, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/3065 (2013.01); H01L 21/3085 (2013.01); H01L 21/3086 (2013.01); H01L 21/823481 (2013.01); H01L 29/6681 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising more than 3 semiconductor fins;
after the forming of the plurality of semiconductor fins, removing an outer semiconductor fin of the plurality of semiconductor fins;
after the removing of the outer semiconductor fin of the plurality of semiconductor fins, epitaxially depositing a semiconductor liner directly on surfaces of the plurality of semiconductor fins;
forming an isolation feature over the semiconductor liner and among the plurality of semiconductor fins; and
forming a gate structure over the plurality of semiconductor fins and over a top surface of the isolation feature,
wherein the removing recesses a portion of the substrate directly under the outer semiconductor fin,
wherein a width of the outer semiconductor fin is greater than a width of any of the rest of the plurality of semiconductor fins.