US 12,283,521 B2
Methods of forming spacers for semiconductor devices including backside power rails
Li-Zhen Yu, New Taipei (TW); Huan-Chieh Su, Tianzhong Township (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 23, 2024, as Appl. No. 18/420,209.
Application 18/420,209 is a continuation of application No. 17/812,902, filed on Jul. 15, 2022, granted, now 11,915,972.
Application 17/812,902 is a continuation of application No. 17/092,773, filed on Nov. 9, 2020, granted, now 11,456,209, issued on Sep. 27, 2022.
Claims priority of provisional application 63/059,222, filed on Jul. 31, 2020.
Prior Publication US 2024/0186179 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/02603 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/5286 (2013.01); H01L 23/5329 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first transistor structure, the first transistor structure comprising a first source/drain region;
a front-side interconnect structure on a front-side of the first transistor structure; and
a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure comprising:
a first dielectric layer on the backside of the first transistor structure;
a first via extending through the first dielectric layer, the first via being electrically coupled to the first source/drain region of the first transistor structure;
a first conductive line electrically coupled to the first via;
a second dielectric layer adjacent the first conductive line; and
an air gap between the second dielectric layer and the first dielectric layer.