US 12,283,519 B2
Forming method for semiconductor structure and semiconductor structure
Chuxian Liao, Hefei (CN); Yuhan Zhu, Hefei (CN); and Zhan Ying, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Jan. 12, 2022, as Appl. No. 17/573,775.
Application 17/573,775 is a continuation of application No. PCT/CN2021/095606, filed on May 24, 2021.
Claims priority of application No. 202010674232.0 (CN), filed on Jul. 14, 2020.
Prior Publication US 2022/0139763 A1, May 5, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/76831 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A forming method for a semiconductor structure, comprising:
providing a substrate, wherein bit line structures are formed on the substrate;
forming a first sacrificial layer on sidewalls of the bit line structures;
forming an isolation layer on a sidewall of the first sacrificial layer;
forming first dielectric layers filling gaps between the bit line structures;
patterning the first dielectric layers to form vias, wherein the vias expose active regions of the substrate, and the vias and remaining parts of the first dielectric layers are alternately arranged in an extension direction of the bit line structures;
forming a second sacrificial layer on sidewalls of the vias, and filling the vias to form contact plugs;
forming contact structures on the contact plugs; and
removing the first sacrificial layer to form first air gaps, and removing the second sacrificial layer to form second air gaps; wherein the second air gaps surrounds the contact structures and the second air gaps are located on the substrate; and,
wherein the first air gaps and the second air gaps are respectively located on two opposite sides of the isolation layer; and
forming the first sacrificial layer on the sidewalls of the bit line structures and forming the isolation layer on the sidewall of the first sacrificial layer comprise:
forming a first sacrificial film on sidewalls of the bit line structures and a surface of the substrate;
forming an isolation film on the sidewall of the first sacrificial film and a surface of a part of the first sacrificial film on the surface of the substrate; and
removing the part of the first sacrificial film on the surface of the substrate and a part of the isolation film on the surface of the substrate to form the isolation layer and the first sacrificial layer, wherein a part of the first sacrificial layer is located at a bottom of the isolation layers, wherein a part of the first air gaps is located at the bottom of the isolation layers, and the first air gaps communicate with the second air gaps.