| CPC H01L 21/76229 (2013.01) [H01L 21/31053 (2013.01); H01L 21/7681 (2013.01); H10D 62/115 (2025.01)] | 8 Claims |
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1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises an array region and a peripheral region, word line structures and first shallow trench isolation structures are formed in the array region, grooves are formed over the word line structures, and a second shallow trench isolation structure is formed in the peripheral region;
forming a patterned mask layer over the semiconductor substrate, wherein the mask layer covers surfaces of the first shallow trench isolation structures and the second shallow trench isolation structure, and the grooves over the word line structures are exposed from the mask layer;
depositing at least two insulating layers on a surface of the semiconductor substrate, and the at least two insulating layers having different etching rates under a same etching condition;
removing a part of the at least two insulating layers located on surfaces of the array region and the peripheral region sequentially, wherein a lower insulating layer is an etching stop layer of an upper insulating layer between the two adjacent insulating layers, and retaining all the at least two insulating layers in the grooves located over the word line structures;
wherein the depositing the at least two insulating layers on the surface of the semiconductor substrate comprises the following steps:
depositing a first insulating layer on a surface of the patterned mask layer and in the grooves over the word line structures;
depositing a second insulating layer on a surface of the first insulating layer; and
depositing a third insulating layer on a surface of the second insulating layer the first insulating layer, the second insulating layer, and the third insulating layer filling in the grooves over the word line structures.
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