US 12,283,512 B2
Semiconductor processing method and apparatus
Shuang-Shiuan Deng, Hsinchu (TW); Fan-Chi Lin, Hsinchu (TW); Chueh-Chi Kuo, Hsinchu (TW); Li-Jui Chen, Hsinchu (TW); and Heng-Hsin Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,519.
Application 18/447,519 is a continuation of application No. 17/477,450, filed on Sep. 16, 2021, granted, now 11,830,754.
Claims priority of provisional application 63/166,460, filed on Mar. 26, 2021.
Prior Publication US 2023/0386884 A1, Nov. 30, 2023
Int. Cl. H01L 21/683 (2006.01); H01L 21/687 (2006.01)
CPC H01L 21/6833 (2013.01) [H01L 21/68721 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a chamber;
an electrostatic chuck;
a first voltage source;
a second voltage source; and
a controller operable to execute instructions, the controller in operation:
securing a first wafer region of a wafer to a first chuck region of the electrostatic chuck by applying a first voltage at a first time, the first voltage being generated by the first voltage source; and
securing a second wafer region of the wafer to a second chuck region of the electrostatic chuck by applying a second voltage at a second time that follows the first time, wherein the second time is during a period in which a first chuck electrode of the first chuck region is partially charged to a voltage level that is less than a voltage level of the first voltage, the second voltage being generated by the second voltage source.