US 12,283,428 B2
Ceramic electronic device and manufacturing method of the same
Yoichi Kato, Takasaki (JP)
Assigned to TAIYO YUDEN CO., LTD., Tokyo (JP)
Filed by TAIYO YUDEN CO., LTD., Tokyo (JP)
Filed on Nov. 6, 2023, as Appl. No. 18/502,926.
Application 18/502,926 is a continuation of application No. 17/694,148, filed on Mar. 14, 2022, granted, now 11,848,157.
Claims priority of application No. 2021-061221 (JP), filed on Mar. 31, 2021.
Prior Publication US 2024/0079181 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01G 4/12 (2006.01); C04B 35/64 (2006.01); H01G 4/008 (2006.01); H01G 4/012 (2006.01); H01G 4/30 (2006.01)
CPC H01G 4/1218 (2013.01) [C04B 35/64 (2013.01); H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A ceramic electronic device comprising:
a multilayer chip in which a plurality of internal electrode layers and a plurality of dielectric layers are alternately stacked, respectively,
wherein the plurality of internal electrode layers are respectively exposed alternately at a first surface of the multilayer chip and a second surface of the multilayer chip,
wherein a section, in which all internal electrode layers constituted by a first set of internal electrode layers exposed at the first surface face and a second set of internal electrode layers exposed at the second surface overlap each other as viewed in a stacking direction, is defined as a capacity section,
wherein, in the capacity section, the plurality of dielectric layers are at least three dielectric layers, each dielectric layer including Sn,
wherein a dielectric layer having a smaller Sn concentration is closer to an outermost end in the stacking direction than is a dielectric layer having a larger Sn concentration which is located at a center area in the stacking direction, in a relationship of at least two of the at least three dielectric layers in the capacity section.