US 12,283,347 B2
Word line driver and memory device
Luguang Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 29, 2022, as Appl. No. 17/936,823.
Application 17/936,823 is a continuation of application No. PCT/CN2022/104755, filed on Jul. 8, 2022.
Claims priority of application No. 202210730432.2 (CN), filed on Jun. 24, 2022.
Prior Publication US 2023/0026502 A1, Jan. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/08 (2006.01); G11C 11/408 (2006.01)
CPC G11C 8/08 (2013.01) [G11C 11/4085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A word line driver comprising:
a substrate comprising an NMOS (N-Metal-Oxide-Semiconductor) area and a PMOS (P-Metal-Oxide-Semiconductor) area;
wherein the PMOS area comprises a plurality of first active areas extending along a first direction, and each first active area comprises a first channel area, and a first source area and a first drain area respectively located on opposite sides of the first channel area,
wherein the NMOS area and the PMOS area are arranged along a second direction, the NMOS area comprises a plurality of second active areas extending along the first direction, each second active area comprises a second channel area, and a second source area and a second drain area respectively located on opposite sides of the second channel area, and the each second active area further comprises a third channel area, and a third source area and a third drain area respectively located on opposite sides of the third channel area;
first gates, wherein the first gates are electrically connected to a main word line, one of the first gates, a first source area and a first drain area constitute a pull-up transistor, the one of the first gates, a second source area and a second drain area constitute a pull-down transistor, the pull-up transistor and the pull-down transistor are electrically connected to a same sub word-line, and an extension direction of first gates corresponding to a first active area are inclined compared with the first direction; and
a plurality of second gates, wherein each second gate covers a corresponding third channel area, and a second gate, a third source area and a third drain area constitute a holding transistor,
wherein, for a same holding transistor, a third drain area is electrically connected to a second drain area of a pull-down transistor and a third source area is electrically connected to a second drain area of another pull-down transistor.