US 12,283,346 B2
Locally embedded bad sector marking for a memory
Stefano Sivero, Comun Nuovo (IT)
Assigned to FERRORELECTRIC MEMORY GMBH, Dresden (DE)
Filed by Ferroelectric Memory GmbH, Dresden (DE)
Filed on May 6, 2022, as Appl. No. 17/662,382.
Prior Publication US 2023/0360684 A1, Nov. 9, 2023
Int. Cl. G11C 11/22 (2006.01); G11C 8/08 (2006.01)
CPC G11C 8/08 (2013.01) 18 Claims
OG exemplary drawing
 
1. A memory arrangement comprising:
a group of memory cells; and
a driver circuit for operating the group of memory cells, wherein the driver circuit comprises a remanent-polarizable memory element and operating transistors, wherein the operating transistors are configured to set a memory state of the remanent-polarizable memory element, and
wherein the driver circuit is configured to enable or disable an operation of the group of memory cells based on the memory state of the remanent-polarizable memory element.