US 12,283,345 B2
Pulse generator, error check and scrub (ECS) circuit and memory
Zequn Huang, Hefei (CN); and Kai Sun, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 8, 2023, as Appl. No. 18/166,034.
Application 18/166,034 is a continuation of application No. PCT/CN2022/112053, filed on Aug. 12, 2022.
Claims priority of application No. 202210901663.5 (CN), filed on Jul. 28, 2022.
Prior Publication US 2024/0038282 A1, Feb. 1, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 29/52 (2006.01)
CPC G11C 7/1093 (2013.01) [G11C 7/1087 (2013.01); G11C 29/52 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A pulse generator, comprising:
a delay circuit, configured to receive an Error Check and Scrub (ECS) command signal, perform delay processing on the ECS command signal, and output a delay command signal, a delay between the ECS command signal and the delay command signal being a first preset value; and
a latch circuit, configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal;
wherein a pulse width of the ECS command signal is provided with a plurality of values, and a pulse width of the ECS pulse signal is the first preset value;
wherein the latch circuit comprises a first NOR gate and a second NOR gate;
wherein a first input end of the first NOR gate receives the ECS command signal, a second input end of the first NOR gate is connected to an output end of the second NOR gate, a first input end of the second NOR gate is connected to an output end of the first NOR gate, a second input end of the second NOR gate receives the delay command signal, and a third input end of the second NOR gate receives the reset signal; and
the output end of the second NOR gate is configured to output the ECS pulse signal.