US 12,283,342 B2
Apparatuses and methods for input buffer data feedback equalization circuits
Kohei Nakamura, Tokyo (JP); and Shuichi Tsukada, Kanagawa (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Nov. 15, 2022, as Appl. No. 18/055,588.
Prior Publication US 2024/0161791 A1, May 16, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/02 (2006.01); G11C 7/14 (2006.01)
CPC G11C 7/106 (2013.01) [G11C 7/02 (2013.01); G11C 7/14 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a data terminal configured to receive a series of voltages which represent a logical state of a series of bits;
a latch configured to compare one of the series of voltages to a threshold voltage and latch a logical value of one of the series of bits based on the comparison, wherein the threshold voltage is based, at least in part, on a capacitance of a node of the latch; and
a data feedback equalization circuit configured to set the threshold voltage based on a value of a previous of the series of bits, wherein the DFE circuit includes:
a plurality of capacitors;
a plurality of transistors configured to couple a respective one of the plurality of capacitors to the node of the latch when active, wherein the plurality of transistors are coupled in parallel between the node and the associated one of the plurality of capacitors, wherein selected ones of the plurality of transistors are activated based on a DFE code.