| CPC G11C 7/1009 (2013.01) [G11C 7/106 (2013.01); G11C 7/1069 (2013.01); G11C 7/222 (2013.01)] | 20 Claims |

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1. A method of operating a memory device, comprising:
receiving a command to read data from a memory structure of the memory device;
latching a bit pattern of the data from the memory structure to a data register based on the received command;
generating a clock mask based on the bit pattern latched to the data register;
detecting a read enable signal on a read enable interface of the memory device;
gating the read enable signal based on the clock mask; and
latching bit values to an input/output (I/O) interface of the memory device in accordance with the gated read enable signal.
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