US 12,283,338 B2
Global data line of multi-array synchronous random access memory (SRAM)
Hee Choul Park, San Jose, CA (US); and Bin Xie, San Jose, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 6, 2022, as Appl. No. 18/076,388.
Claims priority of provisional application 63/336,918, filed on Apr. 29, 2022.
Prior Publication US 2023/0352062 A1, Nov. 2, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/067 (2013.01) [G11C 7/1039 (2013.01); G11C 7/12 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a single-rail static-operation global data line of a synchronous random access memory (SRAM); and
one or more automatic three-state drivers coupled to the single-rail static operation global data line of the SRAM,
wherein the one or more automatic three-state drivers includes:
a first automatic three-state driver coupled to the single-rail static-operation global data line of the SRAM;
a first sense amplifier directly coupled to the first automatic three-state driver;
a first bit line directly coupled to the first sense amplifier and directly coupled to the first automatic three state driver;
a second automatic three state driver coupled to the single-rail static-operation global data line of the SRAM;
a second sense amplifier directly coupled to the second automatic three-state driver; and
a second bit line directly coupled to the second sense amplifier and directly coupled to the second automatic three state driver.