US 12,283,337 B2
Sense amplifier with reduced voltage offset
Yorinobu Fujino, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 28, 2022, as Appl. No. 17/587,163.
Claims priority of provisional application 63/230,518, filed on Aug. 6, 2021.
Prior Publication US 2023/0037885 A1, Feb. 9, 2023
Int. Cl. G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/062 (2013.01) [G11C 7/12 (2013.01); G11C 7/22 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A sense amplifier, comprising:
a first pair of cross-coupled transistors coupled to a first port and a second port of the sense amplifier;
a second pair of cross-coupled transistors coupled to the first port and the second port;
a first access transistor coupled between a first input line and the first port;
a second access transistor coupled between a second input line and the second port;
an enable transistor configured to enable or disable current through the first pair of cross-coupled transistors and the second pair of cross-coupled transistors; and
a delay circuit coupled between i) a gate electrode of the enable transistor and ii) a gate electrode of the first access transistor and a gate electrode of the second access transistor, the delay circuit configured to delay a time to disable the first access transistor and the second access transistor with respect to a time to enable the enable transistor,
wherein a first transistor of the first pair of cross-coupled transistors is directly coupled to the first input line, and
wherein a second transistor of the first pair of cross-coupled transistors is directly coupled to the second input line.