US 12,283,334 B2
Method and apparatus for memory testing
Shih-Hung Chen, Hsinchu (TW)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/366,690.
Claims priority of application No. 112109420 (TW), filed on Mar. 14, 2023.
Prior Publication US 2024/0312556 A1, Sep. 19, 2024
Int. Cl. G11C 29/56 (2006.01)
CPC G11C 29/56016 (2013.01) 16 Claims
OG exemplary drawing
 
1. A memory testing method, comprising:
using a test program group comprising N test programs to test M dies respectively to generate independent N test data, wherein N and M are positive integers greater than 1; and
performing a neural network operation on the N test data to estimate a yield of the M dies passing the test program group,
wherein each of the N test data comprises M sub-test data respectively corresponding to the M dies,
wherein performing the neural network operation on the N test data to estimate the yield of the M dies passing the test program group comprises:
decoding the M sub-test data of each of the N test data to obtain N repair address data respectively corresponding to the N test programs;
obtaining N die test information respectively corresponding to the N test programs according to the N repair address data; and
calculating sequentially a staged yield of each of the N test programs according to the N die test information based on a test sequence,
wherein based on the test sequence, calculating sequentially the staged yield of each of the N test programs according to the N die test information comprises:
analyzing the N die test information to obtain a plurality of pass dies and repair numbers of each of the pass dies after the M dies passing each of the N test programs; and
using the pass dies corresponding to a first test program in the test sequence as an initial common pass die group, and calculating a staged yield of the first test program according to the number of the pass dies in the common pass die group.