US 12,283,333 B2
Bit retiring to mitigate bit errors
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 19, 2024, as Appl. No. 18/640,651.
Application 18/640,651 is a continuation of application No. 17/580,329, filed on Jan. 20, 2022, granted, now 11,990,200.
Claims priority of provisional application 63/142,781, filed on Jan. 28, 2021.
Prior Publication US 2024/0265991 A1, Aug. 8, 2024
Int. Cl. G11C 29/44 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 29/1201 (2013.01); G11C 29/18 (2013.01); G11C 29/42 (2013.01); G11C 2029/1806 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining that a first set of bits retrieved from a first row of a memory array includes one or more errors;
remapping a portion of the first row from a first row index to a second row index based at least in part on determining that the first set of bits includes the one or more errors, wherein the second row index, before remapping the first row, corresponds to a second row of the memory array;
determining that a second set of bits retrieved from a third row of the memory array includes one or more errors, wherein the third row corresponds to a third row index; and
selecting, for remapping a portion of the third row from the third row index based at least in part on determining that the second set of bits includes one or more errors, a fourth row index based at least in part on the fourth row index being subsequent to the second row index remapped to the portion of the first row, wherein the fourth row index, before remapping the third row, corresponds to a fourth row of the memory array.