US 12,283,332 B2
Memory BIST circuit and method
Devanathan Varadarajan, Allen, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 22, 2022, as Appl. No. 18/057,801.
Prior Publication US 2024/0170083 A1, May 23, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/1201 (2013.01) [G11C 29/18 (2013.01); G11C 29/46 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An electronic circuit comprising:
a memory comprising a data input, an address input, a command input, and a data output;
a register comprising a data input and a data output, the data input coupled to the data output of the memory;
a comparator circuit comprising a first data input coupled to the data output of the memory, and a second data input coupled to the data output of the register;
an inverter circuit comprising a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; and
a controller comprising a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, wherein the controller is configured to determine whether the memory has a fault based on the fault input of the controller.