US 12,283,330 B2
Memory system
Tsukasa Tokutomi, Kamakura Kanagawa (JP); Masanobu Shirakawa, Chigasaki Kanagawa (JP); Kiwamu Watanabe, Kawasaki Kanagawa (JP); and Kengo Kurose, Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jul. 18, 2023, as Appl. No. 18/354,300.
Application 18/354,300 is a division of application No. 17/476,229, filed on Sep. 15, 2021, granted, now 11,756,642.
Application 17/476,229 is a division of application No. 16/294,185, filed on Mar. 6, 2019, granted, now 11,152,075, issued on Oct. 19, 2021.
Claims priority of application No. 2018-172913 (JP), filed on Sep. 14, 2018.
Prior Publication US 2023/0360714 A1, Nov. 9, 2023
Int. Cl. G11C 29/12 (2006.01); G06F 3/06 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G11C 29/12 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory comprising a plurality of memory cells and a word line connected to the plurality of memory cells; and
a memory controller configured to repeat a patrol operation in a first period, the patrol operation including a read operation of the plurality of memory cells, wherein
the first period includes a second period and a third period, the third period having a same length as the second period and following the second period,
the second period includes a period immediately after data is written in the memory cell, and
a number of repeating the patrol operation selecting the word line in the second period is different from that in the third period.