US 12,283,326 B2
Memory cell and array structure of non-volatile memory and associated control method
Wei-Ming Ku, Hsinchu County (TW)
Assigned to EMEMORY TECHNOLOGY INC., Hsin-Chu (TW)
Filed by eMemory Technology Inc., Hsin-Chu (TW)
Filed on Feb. 24, 2023, as Appl. No. 18/113,675.
Claims priority of provisional application 63/318,805, filed on Mar. 11, 2022.
Prior Publication US 2023/0290414 A1, Sep. 14, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 16/0408 (2013.01); G11C 16/26 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An array structure of a non-volatile memory, the array structure comprising a first memory cell, the first memory cell comprising:
a first select transistor, wherein a first drain/source terminal of the first select transistor is connected with a source line, and a gate terminal of the first select transistor is connected with a first word line;
a first floating gate transistor, wherein a first drain/source terminal of the first floating gate transistor is connected with a second drain/source terminal of the first select transistor, and a second drain/source terminal of the first floating gate transistor is connected with a first bit line;
a first capacitor, wherein a first terminal of the first capacitor is connected with a floating gate of the first floating gate transistor, and a second terminal of the first capacitor is connected with a first erase node;
a first switching transistor, wherein a first drain/source terminal of the first switching transistor is connected with the first erase node, a second drain/source terminal of the first switching transistor is connected with a first erase line, and a gate terminal of the first switching transistor is connected with a control line; and
a second capacitor, wherein a first terminal of the second capacitor is connected with the first erase node, and a second terminal of the second capacitor is connected with a first boost line.