US 12,283,325 B2
Memory device and operating method of the memory device for controlling program operation
Jae Woong Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 28, 2022, as Appl. No. 18/070,199.
Claims priority of application No. 10-2022-0083292 (KR), filed on Jul. 6, 2022.
Prior Publication US 2024/0013838 A1, Jan. 11, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/3459 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block including a plurality of pages, each page from the plurality of pages including memory cells, the memory cells configured to be programmed to different program states according to a plurality of target voltages; and
a peripheral circuit configured to perform a program operation of a selected page among the plurality of pages,
wherein the peripheral circuit is configured to:
decrease at least one target voltage among the plurality of target voltages to a corresponding sub-target voltage in the program operation of the selected page;
perform the program operation of the selected page according to the other target voltages except the at least one target voltage corresponding to the corresponding sub-target voltage among the target voltages and the corresponding sub-target voltage;
perform a program operation of a page adjacent to the selected page when the program operation of the selected page is ended; and
perform an additional program operation of memory cells programmed according to the corresponding sub-target voltage in the selected page according to the at least one target voltage corresponding to the corresponding sub-target voltage when the program operation of the adjacent page is ended.